Method of fabricating semiconductor structure

ABSTRACT

A method includes the following steps. A semiconductor wafer including integrated circuit components, seal rings respectively encircling the integrated circuit components and testing structures disposed between the seal rings is provided. A first wafer saw process is performed at least along a first path to singulate the semiconductor wafer into a plurality of first singulated integrated circuit components each including a testing structure among the testing structures. When performing the first wafer saw process, testing pads of the testing structures are located beside the first path, such that a testing pad of a corresponding one of the testing structures in the first singulated integrated circuit component is laterally spaced apart from a sidewall of the first singulated integrated circuit component by a distance.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a continuation application of and claims thepriority benefit of a prior application Ser. No. 16/919,073, filed onJul. 1, 2020 and now allowed. The prior application Ser. No. 16/919,073claims the priority benefit of U.S. provisional application Ser. No.62/927,705, filed on Oct. 30, 2019. The entirety of the above-mentionedpatent applications is hereby incorporated by reference herein and madea part of this specification.

BACKGROUND

The semiconductor industry has experienced rapid growth due tocontinuous improvements in the integration density of a variety ofelectronic components (e.g., transistors, diodes, resistors, capacitors,etc.). For the most part, this improvement in integration density hascome from repeated reductions in minimum feature size (e.g., shrinkingthe semiconductor process node towards the sub-20 nm node), which allowsmore components to be integrated into a given area. As the demand forminiaturization, higher speed and greater bandwidth, as well as lowerpower consumption and latency has grown recently, there has grown a needfor smaller and more creative packaging techniques of semiconductordies.

As semiconductor technologies further advance, stacked and bondedsemiconductor devices have emerged as an effective alternative tofurther reduce the physical size of a semiconductor device. In a stackedsemiconductor device, active circuits such as logic, memory, processorcircuits and the like are fabricated at least partially on separatesubstrates and then physically and electrically bonded together in orderto form a functional device. Such bonding processes utilizesophisticated techniques, and improvements are desired.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure are best understood from the followingdetailed description when read with the accompanying figures. It isnoted that, in accordance with the standard practice in the industry,various features are not drawn to scale. In fact, the dimensions of thevarious features may be arbitrarily increased or reduced for clarity ofdiscussion.

FIGS. 1A, 1C and 1D are cross-sectional views schematically illustratinga process flow for fabricating top semiconductor dies in accordance withsome embodiments of the present disclosure. FIG. 1B is a top viewschematically illustrating the integrated circuit components, the ringseals, and the testing structure illustrated in FIG. 1A, in accordancewith some embodiments of the present disclosure.

FIGS. 2A, 2C and 2D are cross-sectional views schematically illustratinga process flow for fabricating top semiconductor dies in accordance withsome other embodiments of the present disclosure. FIG. 2B is a top viewschematically illustrating the integrated circuit components, the ringseals, and the testing structure illustrated in FIG. 2A, in accordancewith some embodiments of the present disclosure.

FIGS. 3A, 3C and 3D are cross-sectional views schematically illustratinga process flow for fabricating top semiconductor dies in accordance withsome other embodiments of the present disclosure. FIG. 3B is a top viewschematically illustrating the integrated circuit components, the ringseals, and the testing structure illustrated in FIG. 3A, in accordancewith some embodiments of the present disclosure.

FIGS. 4A, 4C and 4D are cross-sectional views schematically illustratinga process flow for fabricating top semiconductor dies in accordance withsome other embodiments of the present disclosure. FIG. 4B is a top viewschematically illustrating the integrated circuit components, the ringseals, and the testing structure illustrated in FIG. 4A, in accordancewith some embodiments of the present disclosure.

FIG. 5A through FIG. 5H are cross-sectional views schematicallyillustrating a process flow for fabricating a package structure ofsystem on an integrated circuit (SoIC) chip in accordance with someembodiments of the present disclosure.

FIGS. 6A through 6D are enlarged views of the region X illustrated inFIG. 5H in accordance with various embodiments of the presentdisclosure.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, orexamples, for implementing different features of the provided subjectmatter. Specific examples of components and arrangements are describedbelow to simplify the present disclosure. These are, of course, merelyexamples and are not intended to be limiting. For example, the formationof a first feature over or on a second feature in the description thatfollows may include embodiments in which the first and second featuresare formed in direct contact, and may also include embodiments in whichadditional features may be formed between the first and second features,such that the first and second features may not be in direct contact. Inaddition, the present disclosure may repeat reference numerals and/orletters in the various examples. This repetition is for the purpose ofsimplicity and clarity and does not in itself dictate a relationshipbetween the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,”“above,” “upper” and the like, may be used herein for ease ofdescription to describe one element or feature's relationship to anotherelement(s) or feature(s) as illustrated in the figures. The spatiallyrelative terms are intended to encompass different orientations of thedevice in use or operation in addition to the orientation depicted inthe figures. The apparatus may be otherwise oriented (rotated 90 degreesor at other orientations) and the spatially relative descriptors usedherein may likewise be interpreted accordingly.

Other features and processes may also be included. For example, testingstructures may be included to aid in the verification testing of the 3Dpackaging or 3DIC devices. The testing structures may include, forexample, test pads formed in a redistribution layer or on a substratethat allows the testing of the 3D packaging or 3DIC, the use of probesand/or probe cards, and the like. The verification testing may beperformed on intermediate structures as well as the final structure.Additionally, the structures and methods disclosed herein may be used inconjunction with testing methodologies that incorporate intermediateverification of known good dies to increase the yield and decreasecosts.

Fabrication of Top Semiconductor Dies

FIGS. 1A, 1C and 1D are cross-sectional views schematically illustratinga process flow for fabricating top semiconductor dies in accordance withsome embodiments of the present disclosure. FIG. 1B is a top viewschematically illustrating the integrated circuit components, the ringseals, and the testing structure illustrated in FIG. 1A, in accordancewith some embodiments of the present disclosure. For illustrationpurpose, sawing paths for a wafer sawing process are also shown in FIG.1B. In some embodiments, one integrated circuit component is shown torepresent plural integrated circuit components of the semiconductorwafer.

Referring to FIG. 1A and FIG. 1B, a semiconductor wafer 100A isprovided. The semiconductor wafer 100A may include a semiconductorsubstrate 110 a, integrated circuit components 120, seal rings 130 andtesting structures 140. The integrated circuit components 120 may beformed in and/or on the semiconductor substrate 110 a and may bearranged along X direction and/or Y direction. The seal rings 130 mayrespectively encircle the integrated circuit components 120. The testingstructures 140 may be disposed between the seal rings 130. In someembodiments, each of the integrated circuit components 120 includes aplurality of interconnect wirings 122, a through substrate via (TSV)124, a conductive pad 126 and integrated circuit devices (not shown).

The integrated circuit devices of the integrated circuit component 120may be formed in and/or on the semiconductor substrate 110 a. Theintegrated circuit devices of the integrated circuit component 120 mayinclude active components (e.g., transistors or the like) and/or passivecomponents (e.g., resistors, capacitors, inductors, or the like).

The interconnect wirings 122 of the integrated circuit component 120 maybe formed over the semiconductor substrate 110 a and may be electricallyconnected to the integrated circuit devices of the integrated circuitcomponent 120. The integrated circuit devices may be interconnected bythe interconnect wirings 122 to form an integrated circuit. Theinterconnect wirings 122 of the integrated circuit component 120 may beembedded in a dielectric layer 150 a of the semiconductor wafer 100A. Insome embodiments, the interconnect wirings 122 may be formed of copper,copper alloys or other suitable conductive material. In someembodiments, the material of the dielectric layer 150 a may includesilicon oxide (SiO_(x), where x>0), silicon nitride (SiN_(x), wherex>0), silicon oxynitirde (SiO_(x)N_(y), where x>0 and y>0) or othersuitable dielectric materials.

The through substrate via (TSV) 124 of the integrated circuit component120 may be formed in the semiconductor substrate 110 a and extend intothe dielectric layer 150 a. The through substrate via (TSV) 124 may beelectrically connected to the interconnect wirings 122 of the integratedcircuit component 120. In some embodiments, the amount of the TSV 124may be one or more than one TSVs, and the TSVs 124 may be arranged inlines, columns or arrays. In some embodiments, the TSV 124 may be formedof copper, copper alloys or other suitable conductive material.

The conductive pad 126 of the integrated circuit component 120 may beformed in the dielectric layer 150 a and may be stacked on theinterconnect wirings 122. The conductive pad 126 may be electricallycoupled to the interconnect wirings 122. In some embodiments, materialsof the conductive pad 126 and the interconnect wirings 122 aredifferent. In some embodiments, the conductive pad 126 may be analuminum pad, although other metallic materials may be used.

Each of the seal rings 130 may include a bottom portion 132 and a topportion 134 stacked on the bottom portion 132. The bottom portion 132 ofthe seal ring 130 may encircle the interconnect wirings 122 of theintegrated circuit component 120 therein, and the top portion 134 of theseal ring 130 may encircle the conductive pad 126 of the integratedcircuit component 120 therein. The seal rings 130 can be used as aprotective wall for protecting the integrated circuit components 120from stress. In some embodiments, the seal rings 130 are electricallygrounded or electrically floating. For example, the seal rings 130 maybe electrically insulated from the integrated circuit components 120. Insome embodiments, materials of the bottom portion 132 and the topportion 134 are different.

Each of the testing structures 140 may include a stacked structure 142and a testing pad 144 stacked on the stacked structure 142. In someembodiments, the testing pads 144 of the testing structures 140 areelectrically connected to underlying test devices or test circuits (notshown) through the stacked structures 142. In some embodiments, thetesting pads 144 of the testing structures 140 include process monitorpads, such as wafer acceptance testing (WAT) pads. In some embodiments,before a wafer saw process (e.g., shown in the following FIGS. 1B and1C), a testing process is performed to qualify the integrated circuitcomponents 120 by testing the testing structures 140. During the testingprocess, the testing pads 144 are electrically coupled to an externalterminal through probe needles for testing. The testing pads 144 may beselected to test different properties of the semiconductor wafer 100A,such as leakage current, breakdown voltage, threshold voltage andeffective channel length, saturation current, and so on.

In some embodiments, materials of the stacked structure 142 and thetesting pad 144 are different. In some embodiments, the testing pads 144of the testing structures 140 from the top view may be shaped as arectangular pattern. In some alternative embodiments, the testing padsof the testing structures 140 from the top view may be shaped as acircular pattern. The disclosure does not construe the shape of thetesting pads. In some embodiments, no conductive feature is between theseal rings 130 and the testing structures 140. In other words, thetesting structures 140 are not electrically connected to the integratedcircuit components 120 inside the seal rings 130. For example, thetesting structures 140 are electrically isolated from the interconnectwirings 122, the TSVs 124, the conductive pads 126, and the integratedcircuit devices of the integrated circuit components 120. In FIG. 1B,four testing structures 140 are formed between two adjacent seal rings130. However, the number of the testing structures 140 shown in thefigures is merely exemplary and is not limited thereto. In someembodiments, the pattern density of the stacked structures 142 may rangefrom about 15% to about 40%. The pattern density of the stackedstructures 142 is defined as the ratio of the stacked structure area(i.e., the total area of all the stacked structures 142 therein) to thearea between the seal rings 130.

In some embodiments, the interconnect wirings 122 of the integratedcircuit components 120, the bottom portions 132 of the seal rings 130and the stacked structures 142 of the testing structures 140 areconcurrently formed. In other words, the interconnect wirings 122 of theintegrated circuit components 120, the bottom portions 132 of the sealrings 130 and the stacked structures 142 of the testing structures 140may be formed of the same material and at the same level height (e.g. afirst level height). In some embodiments, the conductive pads 126 of theintegrated circuit components 120, the top portions 134 of the sealrings 130 and the testing pads 144 of the testing structures 140 areconcurrently formed. In other words, the conductive pads 126 of theintegrated circuit components 120, the top portions 134 of the sealrings 130 and the testing pads 144 of the testing structures 140 may beformed of the same material and at the same level height (e.g. a secondlevel height).

As shown in FIG. 1A, the integrated circuit components 120 may furtherinclude a plurality of bonding metallic pads 128. The bonding metallicpads 128 are formed in the dielectric layer 150 a. In some embodiments,some of the bonding metallic pads 128 are electrically connected to theunderlying interconnect wirings 122 through conductive vias 129. In someembodiments, no conductive vias 129 are formed between some of thebonding metallic pads 128 and the interconnect wirings 122. The bondingmetallic pads 128 may be formed of copper, aluminum, nickel, tungsten,or alloys thereof. In some embodiments, the top surface of dielectriclayer 150 a and the top surfaces of bonding metallic pads 128 are levelwith each other, which is achieved through a planarization that isperformed during the formation of the bonding metallic pads 128. Theplanarization may include a chemical mechanical polish (CMP) process.

In some embodiments, after the bonding metallic pads 128 are formed, aback side grinding process is performed on a rear surface of thesemiconductor wafer 100A. During the back side grinding process of thesemiconductor wafer 100A, the semiconductor substrate 110 a is grindedso as to reduce the thickness of the semiconductor wafer 100A.

Referring to FIG. 1B and FIG. 1C, a wafer saw process is performed tosingulate the semiconductor wafer 100A. In some embodiments, akeep-out-zone (KOZ) around the seal ring 130 is imposed to providesawing paths SP (e.g., scribe lines) for the wafer saw process, and thetesting pads 144 of the testing structures 140 are restricted from beingformed within the KOZ. That is, the testing pads 144 of the testingstructures 140 may not be arranged along the sawing paths SP. In otherwords, the sawing paths SP may not be aligned with the testing pads 144of the testing structures 140, and the testing pads 144 of the testingstructures 140 may keep a distance from the sawing paths SP. In someembodiments, the testing pads 144 of the testing structures 140 arelocated between one sawing path SP and an adjacent seal ring 130, and nosawing path SP is between the testing structures 140 and the adjacentseal ring 130. In some embodiments, the stacked structures 142 of thetesting structures 140 are located outside of the KOZ, and the stackedstructures 142 of the testing structures 140 also keep a distance fromthe sawing paths SP. In some embodiments, the KOZ is mesh-shaped, andthe sawing paths SP extending in the X direction and the sawing paths SPextending in the Y direction are aligned with the KOZ.

In some embodiments, as shown in FIG. 1B, the testing structures 140 arelocated beside the sawing paths SP extending in the Y direction and aredistributed in the Y direction. In alternative embodiments, the testingstructures 140 are located beside the sawing paths SP extending in the Xdirection and are distributed in the X direction. In yet alternativeembodiments, some of the testing structures 140 are located beside thesawing paths SP extending in the Y direction and are distributed in theY direction, and some of the testing structures 140 are located besidethe sawing paths SP extending in the X direction and are distributed inthe X direction.

In some embodiments, the wafer saw process involves dicing with arotating blade 210 (in FIG. 1C) to cut through the semiconductor wafer100. When the wafer saw process is performed, the blade 210 cuts intothe semiconductor wafer 100A along the sawing path SP which is alignedwith the KOZ. In some embodiments, the area between the seal rings 130and the testing pads 144 of the testing structures 140 is the KOZ, and awidth W1 of the KOZ is greater than a width W2 of the blade 210. Thewidth W1 of the KOZ may be measured between the sidewall of the topportion 134 of the seal ring 130 and the sidewalls of the testing pads144 of the testing structures 140. That is to say, the testing pads 144of the testing structures 140 are laterally spaced apart from theadjacent seal ring 130 by a distance (i.e., the width W1) greater thanthe width W2 of the blade 210. In some embodiments, the width W2 of theblade 210 may be about 40 micrometers, for example. In some embodiments,the width W1 of the KOZ may be greater than about 40 micrometers orabout 50 micrometers, and less than about 80 micrometers, for example.In some embodiments, the testing structures 140 are spaced apart fromtwo adjacent seal rings 130 at opposite sides by different distances.

As shown in FIG. 1C, the blade 210 is laterally between the sidewall ofthe top portion 134 of the seal ring 130 and the sidewalls of thetesting pads 144 of the testing structures 140 and therefore, does notoverlap or contact the sidewall of the top portion 134 of the seal ring130 and the sidewalls of the testing pads 144 of the testing structures140 during the wafer saw process. Since the blade 210 keeps a distancefrom the testing pads 144 of the testing structures 140 during the wafersaw process, the blade 210 does not cut the testing pads 144 of thetesting structures 140, and the issue of testing pad curling isprevented.

Referring to FIG. 1C and FIG. 1D, the semiconductor wafer 100A issingulated into a plurality of singulated integrated circuit components300A. As illustrated in FIG. 1D, each singulated integrated circuitcomponents 300A may include a semiconductor substrate 110, theintegrated circuit component 120 including the interconnect wirings 122,the TSV 124, the conductive pad 126, the metallic pads 128 and theconductive vias 129, the seal ring 130, the testing structures 140, anda dielectric layer 150. As shown in FIG. 1C and FIG. 1D, the materialsand the characteristics of the semiconductor substrate 110 and thedielectric layer 150 in FIG. 1D are the same as those of thesemiconductor substrate 110 a and the dielectric layer 150 a in FIG. 1C,and the detailed descriptions are omitted therein. In some embodiments,a portion of the seal ring 130 in the singulated integrated circuitcomponent 300A is between the integrated circuit component 120 and thetesting structure 140 in the singulated integrated circuit component300A. In some embodiments, when performing the wafer saw process,testing pads 142 of the testing structures 140 are located beside thesawing paths SP, such that the testing pad 142 of a corresponding one ofthe testing structures 140 in the singulated integrated circuitcomponent 300A is laterally spaced apart from a sidewall SW1 of thesingulated integrated circuit component 300A by a distance. In someembodiments, the stacked structure 142 of the testing structure 140 inthe singulated integrated circuit component 300A is also laterallyspaced apart from the sidewall SW1 of the singulated integrated circuitcomponent 300A. In other words, the testing pad 142 and the stackedstructure 142 of the testing structure 140 may not be revealed at thesidewall SW1 of the singulated integrated circuit component 300A, andmay be still covered by the dielectric layer 150. In some embodiments,no aluminum pad (e.g., the top portions 134 of the seal rings 130 and/orthe testing pad 142 of the testing structure 140) is revealed at thesidewall SW1 of the singulated integrated circuit component 300A.

FIGS. 2A, 2C and 2D are cross-sectional views schematically illustratinga process flow for fabricating top semiconductor dies in accordance withsome other embodiments of the present disclosure. FIG. 2B is a top viewschematically illustrating the integrated circuit components, the ringseals, and the testing structure illustrated in FIG. 2A, in accordancewith some embodiments of the present disclosure. For illustrationpurpose, sawing paths for a wafer sawing process are also shown in FIG.2B. In some embodiments, one integrated circuit component is shown torepresent plural integrated circuit components of the semiconductorwafer.

The process flow shown in FIGS. 2A-2D is similar to the process flowshown in FIGS. 1A-1D, except that another wafer saw process is performedto cut the testing structures 140 from the singulated integrated circuitcomponents.

In FIG. 2A and FIG. 2B, the semiconductor wafer 100B is similar to thesemiconductor wafer 100A of FIG. 1A and FIG. 1B, except that the testingpads 144 of the testing structures 140 are laterally spaced apart fromtwo adjacent seal rings 130 at opposite sides respectively by a distance(i.e., the width W1) greater than the width W2 of the blade 210. In someembodiments, the testing pads 144 of the testing structures 140 arelaterally between two sawing paths SP. In some embodiments, two sawingpaths SP extending in the Y direction are between two adjacent sealrings 130.

In FIG. 2C and FIG. 2D, the semiconductor wafer 100B is singulated intoa plurality of singulated integrated circuit components 300B. When thewafer saw process is performed, the testing structures 140 are cut fromthe semiconductor wafer 100B to obtain the plurality of singulatedintegrated circuit components 300B free of testing structures 140. Inother words, the testing structures 140 are completely removed duringthe wafer saw process. As illustrated in FIG. 2D, each singulatedintegrated circuit components 300B may include the semiconductorsubstrate 110, the integrated circuit component 120 including theinterconnect wirings 122, the TSV 124, the conductive pad 126, themetallic pads 128 and the conductive vias 129, the seal ring 130 and thedielectric layer 150. In some embodiments, the seal ring 130 in thesingulated integrated circuit component 300B is laterally spaced apartfrom a sidewall SW2 of the singulated integrated circuit component 300Bby a distance. In some embodiments, no aluminum pad (e.g., the topportions 134 of the seal rings 130 and/or the testing pad 142 of thetesting structure 140) is revealed at the sidewall SW2 of the singulatedintegrated circuit component 300B.

FIGS. 3A, 3C and 3D are cross-sectional views schematically illustratinga process flow for fabricating top semiconductor dies in accordance withsome other embodiments of the present disclosure. FIG. 3B is a top viewschematically illustrating the integrated circuit components, the ringseals, and the testing structure illustrated in FIG. 3A, in accordancewith some embodiments of the present disclosure. For illustrationpurpose, sawing paths for a wafer sawing process are also shown in FIG.3B. In some embodiments, one integrated circuit component is shown torepresent plural integrated circuit components of the semiconductorwafer.

The process flow shown in FIGS. 3A-3D is similar to the process flowshown in FIGS. 1A-1D, except that a portion of the stacked structures142 of the testing structures 140 are arranged along the sawing path SP,while the testing pads 144 of the testing structures 140 are notarranged along the sawing path SP.

In FIG. 3A and FIG. 3B, the semiconductor wafer 100C is similar to thesemiconductor wafer 100A of FIG. 1A and FIG. 1B, except that a portionof the stacked structures 142 of the testing structures 140 is locatedwithin the KOZ where the testing pads 144 of the testing structures 140are restricted from being formed. In other words, the stacked structures142 of the testing structures 140 are partially overlapped with thesawing path SP.

In FIG. 3C and FIG. 3D, the semiconductor wafer 100C is singulated intoa plurality of singulated integrated circuit components 300C. When thewafer saw process is performed, a portion of the stacked structures 142of the testing structures 140 is cut from the semiconductor wafer 100Cto obtain the plurality of singulated integrated circuit components300C. As illustrated in FIG. 3D, each singulated integrated circuitcomponents 300C may include the semiconductor substrate 110, theintegrated circuit component 120 including the interconnect wirings 122,the TSV 124, the conductive pad 126, the metallic pads 128 and theconductive vias 129, the seal ring 130, a portion 142R1 of the stackedstructures 142, the testing pads 144 and the dielectric layer 150. Insome embodiments, a portion of the seal ring 130 in the singulatedintegrated circuit component 300C is between the integrated circuitcomponent 120 and the testing structure 140 in the singulated integratedcircuit component 300C. In some embodiments, when performing the wafersaw process, testing pads 142 of the testing structures 140 are locatedbeside the sawing paths SP, such that the testing pad 142 of acorresponding one of the testing structures 140 in the singulatedintegrated circuit component 300C is laterally spaced apart from asidewall SW3 of the singulated integrated circuit component 300C by adistance. In other words, the testing pad 142 of the testing structure140 may not be revealed at the sidewall SW3 of the singulated integratedcircuit component 300C, and may be still covered by the dielectric layer150. In some embodiments, the portion 142R1 of the stacked structure 142in the first singulated integrated circuit component 300C is revealed atthe sidewall SW3 of the singulated integrated circuit component 300C. Insome embodiments, the revealed surface of the portion 142R1 of thestacked structure 142 is substantially aligned with the sidewall SW3 ofthe singulated integrated circuit component 300C. In some embodiments,no aluminum pad (e.g., the top portions 134 of the seal rings 130 and/orthe testing pad 142 of the testing structure 140) is revealed at thesidewall SW3 of the singulated integrated circuit component 300C.

FIGS. 4A, 4C and 4D are cross-sectional views schematically illustratinga process flow for fabricating top semiconductor dies in accordance withsome other embodiments of the present disclosure. FIG. 4B is a top viewschematically illustrating the integrated circuit components, the ringseals, and the testing structure illustrated in FIG. 4A, in accordancewith some embodiments of the present disclosure. For illustrationpurpose, sawing paths for a wafer sawing process are also shown in FIG.4B. In some embodiments, one integrated circuit component is shown torepresent plural integrated circuit components of the semiconductorwafer.

The process flow shown in FIGS. 4A-4D is similar to the process flowshown in FIGS. 1A-1D, except that the testing structures 140 arearranged along the sawing path SP, and the testing structures 140 doesnot include the testing pads stacked on the stacked structures 142.

In FIG. 4A and FIG. 4B, the semiconductor wafer 100D is similar to thesemiconductor wafer 100A of FIG. 1A and FIG. 1B, except that the testingstructures 140 do not include the testing pads. In other words, thetesting structures 140 may be free of aluminum pad. In some embodiments,no testing pad is formed on the stacked structures 142 when theconductive pads 126 of the integrated circuit components 120 and the topportions 134 of the seal rings 130 are formed. In some embodiments, thestacked structures 142 of the testing structures 140 is located withinthe KOZ where the testing pads of the testing structures 140 arerestricted from being formed. In some embodiments, the area between theseal rings 130 is the KOZ.

In FIG. 4C and FIG. 4D, the semiconductor wafer 100D is singulated intoa plurality of singulated integrated circuit components 300D. When thewafer saw process is performed, the testing structures 140 (i.e., thestacked structure 142) are arranged along the sawing paths SP and arepartially removed from the semiconductor wafer 100D to obtain theplurality of singulated integrated circuit components 300D havingresidue structures 142R2 of the testing structures 140. As illustratedin FIG. 4D, each singulated integrated circuit components 300D mayinclude the semiconductor substrate 110, the integrated circuitcomponent 120 including the interconnect wirings 122, the TSV 124, theconductive pad 126, the metallic pads 128 and the conductive vias 129,the seal ring 130, the dielectric layer 150 and the residue structures142R2. In some embodiments, the residue structure 142R2 is revealed at asidewall SW4 of the singulated integrated circuit component 300D. Insome embodiments, the residue structures 142R2 are free of testing pad(e.g., aluminum pad), such that no testing pad (e.g., aluminum pad) isrevealed at the sidewall SW4 of the singulated integrated circuitcomponent 300D. In some embodiments, the revealed surface of the residuestructures 142R2 is substantially aligned with the sidewall SW4 of thesingulated integrated circuit component 300D. In some embodiments, noaluminum pad (e.g., the top portions 134 of the seal rings 130 and/orthe testing pad 142 of the testing structure 140) is revealed at thesidewall SW4 of the singulated integrated circuit component 300D.

Fabrication of Package Structure

FIG. 5A through FIG. 5H are cross-sectional views schematicallyillustrating a process flow for fabricating a package structure ofsystem on an integrated circuit (SoIC) chip in accordance with someembodiments of the present disclosure. In some embodiments, oneintegrated circuit component is shown to represent plural integratedcircuit components of the semiconductor wafer, and, and one packagestructure is shown to represent plural package structures obtainedfollowing the manufacturing method.

Referring to FIG. 5A, a semiconductor wafer 400 a is provided. In someembodiment, the semiconductor wafer 400 a includes a semiconductorsubstrate 410 a and a bonding portion 420 a over the semiconductorsubstrate 410 a. The semiconductor substrate 410 a may be a bulk siliconsubstrate, a silicon-on-insulator (SOI) substrate or agermanium-on-insulator (GOI) substrate. The semiconductor substrate 410a may include other suitable semiconductor materials. In someembodiment, the semiconductor substrate 410 a may include activecomponents (e.g., transistors or the like) and/or passive components(e.g., resistors, capacitors, inductors, or the like) formed therein. Insome embodiments, the semiconductor substrate 410 a may includesemiconductor dies embedded therein. The bonding portion 420 a mayinclude a dielectric layer 422 a and metallic pads 424. In someembodiments, the metallic pads 424 are embedded in the dielectric layer422 a, but the top surfaces of the metallic pads 424 are exposed. Thematerial of the dielectric layer 422 a may include silicon oxide(SiO_(x), where x>0), silicon nitride (SiN_(x), where x>0), siliconoxynitirde (SiO_(x)N_(y), where x>0 and y>0) or other suitabledielectric materials. The material of the metallic pads 424 may includecopper, copper alloys or other suitable metallic materials. In someembodiment, a top surface of the dielectric layer 422 a and the topsurfaces of the metallic pads 424 are level with each other, which isachieved through a planarization that is performed during the formationof the metallic pads 424. The planarization may include a chemicalmechanical polish (CMP) process.

Referring to FIG. 5B, multiple top semiconductor dies 300 are providedand bonded to the bonding portion 420 a of the semiconductor wafer 400a. The top semiconductor die 300 may be a qualified singulatedintegrated circuit component among the singulated integrated circuitcomponents 300A, the singulated integrated circuit components 300B, thesingulated integrated circuit components 300C, or the singulatedintegrated circuit components 300D described above. In some embodiments,the qualified singulated integrated circuit component is determinedaccording to the afore-mentioned testing process performed by testingthe testing structures 140. The top semiconductor dies 300 eachincluding the metallic pads 128 and the dielectric layer 150 may beflipped over and pressed onto the bonding portion 420 a of thesemiconductor wafer 400 a such that the metallic pads 128 and thedielectric layer 150 are in contact with the bonding portion 420 a ofthe semiconductor wafer 400 a. A bonding process is performed to bondthe top semiconductor dies 300 to the semiconductor wafer 400 a throughhybrid bonding, wherein the dielectric layers 150 of the topsemiconductor dies 300 are bonded with the dielectric layer 422 a of thesemiconductor wafer 400 a, and the metallic pads 128 of the topsemiconductor dies 300 are bonded with the metallic pads 424 of thesemiconductor wafer 400 a. In detail, the dielectric layers 150 of thetop semiconductor dies 300 and the dielectric layer 422 a of thesemiconductor wafer 400 a are bonded by dielectric-to-dielectricbonding, while the metallic pads 128 of the top semiconductor dies 300and the metallic pads 424 of the semiconductor wafer 400 a are bonded bymetal-to-metal bonding.

Referring to FIG. 5B and FIG. 5C, after the top semiconductor dies 300are bonded to the semiconductor wafer 400 a, an insulating encapsulation510 a is formed over the semiconductor wafer 400 a to laterallyencapsulate the top semiconductor dies 300. The insulating encapsulation510 a may be formed by an over-molding or deposition process followed bya grinding process. In some embodiments, the material of the insulatingencapsulation 510 a includes deposited polyimide, deposited oxide,deposited nitride, or other suitable deposited dielectric material. Insome alternative embodiments, the material of the insulatingencapsulation 510 a includes epoxy or other suitable molding compound.In some embodiments, an insulating material is formed over the bondingportion 420 a of the semiconductor wafer 400 a through an over-moldprocess or a deposition process to cover sidewalls SW and bottomsurfaces BS1 (shown in FIG. 5B) of the top semiconductor dies 300, andthe insulating material is then polished by, for example, a mechanicalgrinding process and/or a CMP process such that the insulatingencapsulation 510 a are formed and the bottom surfaces BS2 (shown inFIG. 5C) of the top semiconductor dies 300 are revealed. During thegrinding process of the insulating material, the semiconductorsubstrates 110 of the top semiconductor dies 300 are polished andthinned down such that bottom surfaces BS3 of the TSVs 124 are revealed.In some embodiments, the bottom surfaces BS3 the TSVs 124 may besubstantially coplanar with the bottom surfaces BS2 of the topsemiconductor dies 300. In some alternative embodiments, not illustratedin FIG. 5C, the TSVs 124 may slightly protrude from the bottom surfacesBS2 of the top semiconductor dies 300.

Referring to FIG. 5C and FIG. 5D, a recessing process is performed toremove portions of the semiconductor substrates 110 of the topsemiconductor dies 300, such that top surfaces BS3 and upper sidewallsUSW of the TSVs 124 are exposed. In other words, the TSVs 124 maypenetrate through the semiconductor substrate 110 of the topsemiconductor dies 300 and protrude from the bottom surface BS4 of thetop semiconductor dies 300. In some embodiments, the semiconductorsubstrates 110 of the top semiconductor dies 300 are recessed byperforming a dry etching process. In some alternative embodiments, notillustrated in FIG. 5D, a portion of the insulating encapsulation 510 ais removed during the recessing process, such that the TSVs 124 areprojected to be higher than top surfaces S1 of insulating encapsulation510 a.

Referring to FIG. 5D and FIG. 5E, an isolation layer 520 is formed tocover the bottom surfaces BS4 of the top semiconductor dies 300, so asto separate the semiconductor substrates 110 of the top semiconductordies 300 from the later-formed overlying redistribution circuit layer.In some embodiments, an isolation dielectric material (not shown) isformed over the bottom surfaces BS4 of the top semiconductor dies 300and the top surface S1 of the insulating encapsulation 510 a, and theisolation dielectric material may be formed by deposition, such as CVDor the like. Then, a planarization process is performed to planarize theisolation dielectric material to form the isolation layer 520. In someembodiments, the isolation dielectric material and the TSVs 124 arepartially removed through polishing or grinding until the bottomsurfaces BS2 of the TSVs 124 are coplanar with the top surface S1 of theinsulating encapsulation 510 a. After the planarization process, theisolation layer 520 covers the bottom surfaces BS4 of the topsemiconductor dies 300 and the upper sidewalls USW of the TSVs 124. Insome embodiments, the isolation dielectric material is planarized byperforming a mechanical grinding process and/or a CMP process. After thepolishing or grinding step, a cleaning step may be optionally performedto clean and remove the residues generated from the grinding orpolishing step. In some alternative embodiments, the insulatingencapsulation 510 a may be slightly grinded or polished during theplanarization process performed to the isolation dielectric material. Insome embodiments, a top surface S2 the solation layer 520 issubstantially levelled with the bottom surfaces BS3 of the TSVs 124 andthe top surface S1 of the insulating encapsulation 510 a after theplanarization process.

In some embodiments, the isolation layer 520 may be made of inorganicmaterials, such as silicon oxide, silicon nitride, silicon oxynitride,or any suitable dielectric material. In some alternative embodiments,the isolation layer 520 may be made of organic materials, such aspolybenzoxazole (PBO), polyimide (PI) or other suitable polymers.

Referring to FIG. 5E and FIG. 5F, conductive through vias 520 may beformed in the insulating encapsulation 510 a. The conductive throughvias 520 may be electrically connected to the semiconductor wafer 400 athrough the metallic pads 424. In some embodiments, through via holesare formed in the insulating encapsulation 510 a by, for example,photolithography and etch processes. A conductive material is depositedover the insulating encapsulation 510 a to fill the through via holes. Aremoval process may be performed to partially remove the depositedconductive material until the insulating encapsulation 510 a are exposedsuch that the conductive through vias 520 are formed in the insulatingencapsulation 510 a. The deposited conductive material for forming theconductive through vias 520 may be partially removed by an etchingprocess, a mechanical grinding process, a CMP process, or other suitableremoval processes, or combinations thereof. For example, a seed layer isformed over the top semiconductor dies 300 and the insulatingencapsulation 510 a through a sputter process, a conductive material isformed over the seed layer through an electro-plating process, and a CMPprocess is then performed to remove the conductive material and the seedlayer outside the through via holes to form the conductive through vias520. The material of the conductive through vias 520 may include copper,copper alloys or other suitable metallic materials.

As illustrated in FIG. 5F, a redistribution circuit layer 530 a andelectrical terminals 540 may be formed over the top semiconductor dies300 and the insulating encapsulant 510 a to be electrically connected tothe top semiconductor dies 300 and the conductive through vias 520. Insome embodiments, the redistribution circuit layer 530 a includes aplurality of dielectric layers and a plurality of redistribution layersstacked alternately. The number of the dielectric layers or theredistribution layers is not limited by the disclosure. In someembodiments, the electrical terminals 540 include controlled collapsechip connection (C4) bumps, micro-bumps, solder balls, ball grid array(BGA) balls, or other suitable terminals for providing externalconnections. Other possible forms and shapes of the electrical terminals540 may be utilized according to design requirements. In someembodiments, a soldering process and a reflow process are optionallyperformed for enhancement of the adhesion between the electricalterminals 540 and the redistribution circuit layer 530 a.

Referring to FIG. 5F and FIG. 5G, after the redistribution circuit layer530 a and electrical terminals 540 are formed, the wafer-level packageincluding the semiconductor wafer 400 a, the top semiconductor dies 300,the insulating encapsulant 510 a, the redistribution circuit layer 530 aand the electrical terminals 540 is flipped upside down and is placed ona tape TP.

Referring to FIG. 5G and FIG. 5H, a wafer dicing process is performed tosingulate the structure mounted on the tape TP. Thereafter, the dicedstructure is removed from the tape TP to form multiple singulated SoICpackages 10. In some embodiments, the wafer dicing process is, forexample, a laser cutting process, a mechanical cutting process, or othersuitable processes. The detailed structure of the singulated SoICpackage 10 will be described in accompany with FIG. 5H.

As illustrated in FIG. 5H, the SoIC package 10 may include a bottomsemiconductor die 400, the top semiconductor dies 300, an insulatingencapsulation 510, the conductive through vias 520, a redistributioncircuit layer 530 and the electrical terminals 540. The bottomsemiconductor die 400 may include a semiconductor substrate 410 and abonding portion 420 over the semiconductor substrate 410. The bondingportion 420 may include a dielectric layer 422 and the metallic pads424. The top semiconductor dies 300 may be over and electricallyconnected to the bottom semiconductor die 400. The insulatingencapsulation 510 may laterally encapsulate the top semiconductor dies300 and the conductive through vias 520. The redistribution circuitlayer 530 may be over and electrically connected to top semiconductordies 300 and the conductive through vias 520. The electrical terminals540 may be over the redistribution circuit layer 530 and electricallyconnected to the top semiconductor dies 300 and the conductive throughvias 520 through the redistribution circuit layer 530. As shown in FIG.5G and FIG. 5H, the materials and the characteristics of the bottomsemiconductor die 400, insulating encapsulation 510 and theredistribution circuit layer 530 in FIG. 5H are the same as those ofsemiconductor wafer 400 a, the insulating encapsulation 510 a and theredistribution circuit layer 530 a in FIG. 5G, and the detaileddescriptions are omitted therein. The SoIC package 10 may include ahybrid bonding interface including dielectric-to-dielectric bondinginterface (i.e. dielectric-to-dielectric bonding interface between thedielectric layer 150 and 422) and metal-to-metal bonding interface (i.e.metal-to-metal bonding interface between the metallic pads 128 and 424).Up to here, the fabrication of the SoIC package 10 is substantiallycomplete.

FIGS. 6A through 6D are enlarged views of the region X illustrated inFIG. 5H in accordance with various embodiments of the presentdisclosure.

Referring to FIGS. 5H and 6A, in an embodiment where the topsemiconductor dies 300 of FIG. 5H are the singulated integrated circuitcomponents 300A of FIG. 1D, the testing structure 140 is spaced apartfrom the insulating encapsulation 510 by a portion of the dielectriclayer 150. In other words, the sidewall SW1 of the singulated integratedcircuit components 300A is between the testing structure 140 and theinsulating encapsulation 510. In some embodiments, the testing structure140 is between the semiconductor substrate 110 of the top semiconductordie 300 and the bonding portion 420 of the bottom semiconductor die 400.In some embodiments, the testing structure 140 is embedded in thedielectric layer 150, and is spaced apart from the bottom semiconductordie 400 by a portion of the dielectric layer 150.

Referring to FIGS. 5H and 6B, in an embodiment where the topsemiconductor dies 300 of FIG. 5H are the singulated integrated circuitcomponents 300B of FIG. 2D, the ring seal 130 is spaced apart from theinsulating encapsulation 510 by a portion of the dielectric layer 150.In other words, the sidewall SW2 of the singulated integrated circuitcomponents 300B is between the ring seal 130 and the insulatingencapsulation 510.

Referring to FIGS. 5H and 6C, in an embodiment where the topsemiconductor dies 300 of FIG. 5H are the singulated integrated circuitcomponents 300C of FIG. 3D, the testing pads 144 of the testingstructure 140 is spaced apart from the insulating encapsulation 510 by aportion of the dielectric layer 150, and the portion 142R1 of thestacked structure 142 is in contact with the insulating encapsulation510. In other words, the sidewall SW3 of the singulated integratedcircuit components 300C is between the testing pads 144 of the testingstructure 140 and the insulating encapsulation 510. In some embodiments,the testing structure 140 is between the semiconductor substrate 110 ofthe top semiconductor die 300 and the bonding portion 420 of the bottomsemiconductor die 400. In some embodiments, the testing structure 140 isembedded in the dielectric layer 150, and is spaced apart from thebottom semiconductor die 400 by a portion of the dielectric layer 150.

Referring to FIGS. 5H and 6D, in an embodiment where the topsemiconductor dies 300 of FIG. 5H are the singulated integrated circuitcomponents 300D of FIG. 4D, the residue structures 142R2 of the testingstructure 140 is in contact with the insulating encapsulation 510. Insome embodiments, the residue structures 142R2 of the testing structure140 is between the semiconductor substrate 110 of the top semiconductordie 300 and the bonding portion 420 of the bottom semiconductor die 400.In some embodiments, the residue structures 142R2 of the testingstructure 140 is embedded in the dielectric layer 150, and is spacedapart from the bottom semiconductor die 400 by a portion of thedielectric layer 150.

Since the blade 210 does not contact and cut the testing pads 144 of thetesting structures 140 during the wafer saw process, the issue oftesting pad curling is prevented. Therefore, the bonding yield of theSoIC chip may be improved.

In accordance with some embodiments of the disclosure, a method includesthe following steps. A semiconductor wafer including integrated circuitcomponents, seal rings respectively encircling the integrated circuitcomponents and testing structures disposed between the seal rings isprovided. A first wafer saw process is performed at least along a firstpath to singulate the semiconductor wafer into a plurality of firstsingulated integrated circuit components each including a testingstructure among the testing structures. When performing the first wafersaw process, testing pads of the testing structures are located besidethe first path, such that a testing pad of a corresponding one of thetesting structures in the first singulated integrated circuit componentis laterally spaced apart from a sidewall of the first singulatedintegrated circuit component by a distance.

In accordance with some embodiments of the disclosure, a method includesthe following steps. A semiconductor wafer including integrated circuitcomponents, seal rings respectively encircling the integrated circuitcomponents and testing structures disposed between the seal rings isprovided. A wafer saw process at least along a path is performed tosingulate the semiconductor wafer into a plurality of singulatedintegrated circuit components. When performing the wafer saw process,the testing structures are arranged along the path, such that each ofthe singulated integrated circuit components includes a residuestructure of a corresponding one of the testing structures, wherein theresidue structure is free of aluminum pad.

In accordance with some embodiments of the disclosure, a device includesa first semiconductor die. The first semiconductor die includes anintegrated circuit component, a seal ring and a testing structure. Theseal ring encircles the integrated circuit component. A portion of theseal ring is between the integrated circuit component and the testingstructure, and the testing structure comprises a testing pad laterallyspaced apart from a sidewall of the first semiconductor die by adistance.

The foregoing outlines features of several embodiments so that thoseskilled in the art may better understand the aspects of the presentdisclosure. Those skilled in the art should appreciate that they mayreadily use the present disclosure as a basis for designing or modifyingother processes and structures for carrying out the same purposes and/orachieving the same advantages of the embodiments introduced herein.Those skilled in the art should also realize that such equivalentconstructions do not depart from the spirit and scope of the presentdisclosure, and that they may make various changes, substitutions, andalterations herein without departing from the spirit and scope of thepresent disclosure.

What is claimed is:
 1. A method, comprising: providing a semiconductorwafer comprising integrated circuit components, seal rings respectivelyencircling the integrated circuit components and testing structuresdisposed between the seal rings; performing a first cutting process atleast along a first path to singulate the semiconductor wafer into aplurality of singulated integrated circuit components each comprising atesting structure among the testing structures, wherein the testingstructures are not cut by a blade used in the first cutting process,such that one testing structure among the testing structures distributedin the singulated integrated circuit component is laterally spaced apartfrom a sidewall of the singulated integrated circuit component; andperforming a second cutting process along a second path between thetesting structures and the seal rings to cut the testing structures fromthe singulated integrated circuit components.
 2. The method as claimedin claim 1, wherein providing the semiconductor wafer comprises: formingstacked structures of the testing structures over a semiconductorsubstrate; and forming the testing pads on the stacked structures. 3.The method as claimed in claim 2, wherein providing the semiconductorwafer further comprises: forming interconnect wirings of the integratedcircuit components over the semiconductor substrate; and formingconductive pads on the interconnect wirings, wherein the interconnectwirings and the stacked structures of the testing structures areconcurrently formed at a first level height, and the conductive pads andthe testing pads of the testing structures are concurrently formed at asecond level height.
 4. The method as claimed in claim 2, whereinmaterials of the testing pads and the stacked structures are different.5. The method as claimed in claim 2, wherein the stacked structures ofthe testing structures are located beside the first path and keep adistance from the first path, such that a stacked structure of thetesting structure in the singulated integrated circuit component islaterally spaced apart from the sidewall of the singulated integratedcircuit component.
 6. The method as claimed in claim 2, wherein thestacked structures of the testing structures are not revealed at thesidewall of the singulated integrated circuit component.
 7. The methodas claimed in claim 1, wherein the first path is laterally spaced apartfrom the second path.
 8. The method as claimed in claim 1, furthercomprising: performing a testing process to qualify the integratedcircuit components by testing the testing structures; and according tothe testing process, bonding a qualified singulated integrated circuitcomponent among the singulated integrated circuit components to asemiconductor device.
 9. The method as claimed in claim 1, wherein thesecond cutting process is performed using a blade.
 10. A method,comprising: providing a semiconductor wafer comprising integratedcircuit components, seal rings respectively encircling the integratedcircuit components and testing structures disposed between the sealrings; performing a first cutting process at least to singulate thesemiconductor wafer into a plurality of singulated integrated circuitcomponents; and performing a second cutting process along a path betweenthe testing structures and the seal rings to remove the testingstructures from the singulated integrated circuit components, whereinthe second cutting process is performed using a blade, and the testingstructures are not in contact with the blade used in the second cuttingprocess.
 11. The method as claimed in claim 10, wherein the testingstructures are not in contact with a blade used in the first cuttingprocess.
 12. The method as claimed in claim 10, wherein providing thesemiconductor wafer further comprises: concurrently forming interconnectwirings of the integrated circuit components and stacked structures ofthe testing structures over a semiconductor substrate at a first levelheight; and forming conductive pads on the interconnect wirings at asecond level height.
 13. The method as claimed in claim 10, furthercomprising: performing a testing process to qualify the singulatedintegrated circuit components by testing the testing structures; andaccording to the testing process, bonding a qualified singulatedintegrated circuit component among the singulated integrated circuitcomponents to a semiconductor device.
 14. A method, comprising:providing a semiconductor wafer comprising integrated circuit componentsand testing structures; and performing a cutting process to singulatethe semiconductor wafer into a plurality of first pieces and a pluralityof second pieces, wherein each of the first pieces respectivelycomprises one integrated circuit component among the integrated circuitcomponents, and each of the second pieces respectively comprises atleast one testing structure among the testing structures, wherein thetesting structures are arranged along a path which is offset from acutting path of the cutting process.
 15. The method as claimed in claim14, wherein performing the cutting process comprises: performing a firstcutting process at least along a first path to singulate thesemiconductor wafer into a plurality of singulated structures, whereineach of the singulated structures respectively comprises one integratedcircuit component among the integrated circuit components and at leastone testing structure among the testing structures; and after performingthe first cutting process, performing a second cutting process along asecond path to cut the testing structures from the singulated structuresto obtain the first pieces and the second pieces.
 16. The method asclaimed in claim 15, wherein during the first cutting process, thetesting structures are not in contact with a blade used in the firstcutting process.
 17. The method as claimed in claim 15, wherein duringthe second cutting process, the testing structures are not in contactwith a blade used in the second cutting process.
 18. The method asclaimed in claim 14, wherein the testing structures in the singulatedstructures are not revealed at sidewalls of the singulated structuresafter performing the first cutting process.
 19. The method as claimed inclaim 14, wherein the testing structures in the pieces are not revealedat sidewalls of the pieces after performing the second cutting process.20. The method as claimed in claim 14, wherein the first cutting processand the second cutting process are performed using a blade.